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Intel Staff Product Reliability Engineer in Santa Clara, California

Job Description

As an integral part of Intel's IDM 2.0 strategy, the Corporate Planning Group (CPG) is established matrix reporting to CEO, to drive world class operational execution and superb centralized planning to address our customers' needs. CPG will accelerate the success of IDM 2.0 and enable business priorities across internal manufacturing, external manufacturing, and support all our customers for growth and success. This new organization will maximize impact with cross BU, TD, and Manufacturing alignment, display independence for our external wafer sourcing and IFS customers and bring us closer together as One Intel.

This position will be part of the CPG Foundry Technology and Engineering (FTE) team chartered with accelerating product leadership through strong collaboration and execution with our 3rd party Foundry, Assembly and Test suppliers. FTE manages Foundry and OSAT to deliver compelling, timely, Intel-aligned technology and enable Intel to leverage it most effectively, leadership product design and manufacturing

FTE seeks a dynamic Staff Product Reliability Engineer responsible for, but not limited to:

  • Drive debug test strategies to improve test stability and yield in manufacturing.

  • Lead key product reliability innovation programs with key internal and external teams and suppliers.

  • Ensure the manufacture reliability of integrated circuits through production ramp for products manufactured at external foundries and Intel internal assembly and test facilities.

  • Analyze the quality and reliability request from internal business unit, and drive reliability implementation with OSAT

  • Autonomously plans and schedules own daily tasks, develops solutions to problems utilizing formal education and judgment.



You must possess the below minimum qualifications to be initially considered for this position. This Position is not eligible for Intel immigration sponsorship

Minimum Qualifications:

  • The candidate must possess a Bachelor's Degree in Electrical engineering or related field of study with 6+ years of experience DFT on products that went into production

  • or Master's degree with 4+ years of experience in DFT on products that went into production.

  • 6+ years of relevant experience writing scripts and small software programs for automation, using RTL and physical design tools, EDA vendor tools such as scan ATPG, memory BIST, industry DFT practices in HSIO test, PLL test, and debug methods and production test equipment.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

US, Arizona, Phoenix;US, California, Folsom

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.