Job Description

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel (https://www.youtube.com/c/Intel/videos) or the links below!

· Life at Intel (https://www.intel.com/content/www/us/en/jobs/life-at-intel.html)

· Diversity at Intel (https://www.intel.com/content/www/us/en/diversity/diversity-at-intel.html)

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone.

You will be part of the Mixed Signal IP Development team chartered to deliver Hi Speed IO (HSIO) IP to the SOC teams across Intel for the latest server, desktop, and mobile products. You will work in a high-performing close-knit vertical team focused on making an impact while fostering employee technical develop and growth.

Your responsibilities will include but are not limited to:

• Perform physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.

• Conduct all aspects of physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, reliability, power and noise analysis.

• Analyze results and recommending fixes to current and future architecture.

• Optimize design to improve product-level parameters such as power, performance, and area.

• Participate in the development and improvement of physical design methodologies and flow automation.

• Partner with the DA team on innovation and initiatives to enhance existing automation, tools, and methodology.

• Conduct verification and signoff including formal equivalence verification, static timing, reliability, power, layout, electrical and structural design rule checks.

• Build and release CBB SHIP packages to internal customers; release IP package into the central IP repository.

• Support internal SoC and IFS customers with (physical and timing) integration of IP.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must possess a Bachelor's degree in Electrical Engineering, Computer Engineering or a related field with 4+ years' experience -OR- a Master's degree in Electrical Engineering, Computer Engineering, or a related field with 3+ years' experience -OR- PhD degree in Electrical Engineering, Computer Engineering, or a related field experience.

Experience in two or more of the following areas:

• Synopsys or Cadence design (RTL to GDS) tools.

• Synopsys-Primetime.

• ICV or Calibre DRC/LVS Layout cleanup.

• Experience with multiple clock domain design.

Preferred Qualifications:

• Synopsys design (RTL to GDS) construction and sign-off tools.

• Experience with low power design, power gating and multiple power domain design.

• Experience with PV methods and history of converging timing on multi clock domain designs.

• Experience with DFT insertions that include MBIST and SCAN.

• Experience with TFM (Tools, Flows, Methodology) Development.

• Experience in Perl, TCL/Tk and/or Python programming.

• Strong analytical ability, problem solving, debugging and communication skills.

• Ability to work independently and at various levels of abstraction.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

Annual Salary Range for jobs which could be performed in US, California: $123,419.00-$185,123.00

*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.