Intel EDA Tools Software Engineer in Santa Clara, California
About the role:
The custom layout team works with internal and external customers to ensure that they are enabled with a productive design environment using Intel's advanced process technologies on external Electronic Design Automation (EDA) tools. Role requires individuals to identify & address custom layout technology file and tool gaps and help drive vendor tool updates.
This includes functioning as an interface between end-users and EDA suppliers. Some key responsibilities include the following:
Deploying and testing efficiency of tools in achieving design goals and collaborating with design teams on methodology development.
Development of automated flows involving writing efficient code in scripting languages to automatically translate Intel process technology rules and requirements into vendor specific technology library file formats.
Design Automation Engineers are advocates of applying design methodologies to help execute projects effectively and successfully with high quality.
About the team:
This is EDA Tools Software Engineering position in the Custom Layout Team of the Process Design Kit (PDK) group, within the Design Enablement (DE) organization.
Excellent opportunity for individuals who enjoy working in fast paced team environment. Highly visible role requiring excellent communication skills with ability to identify bottlenecks, critical paths and develop mitigation plans to manage risk, resources, and timelines for successful PDK delivery.
Individuals will manage development and support of Custom Layout technology/foundry rule files for PDK component on Intel process nodes and drive milestones and associated tasks towards successful execution. Individual will own tasks and also work through other members/teams to plan, execute and deploy necessary collaterals to support multi-vendor custom layout technology offering. Individuals will be responsible for driving internal/external customer tickets to resolution as per DE guidelines.
Important behavior traits we look for:
Versatile Team player
Behavioral history with respect to quality
Critical thinker with problem-solving skills
Bachelors or Master's degree in Electrical Engineering, Computer Science, Computer Engineering or related field with 4+ years of industry experience is required in the following areas:
Custom Layout tools and Technology file development (Virtuoso or Custom Compiler)
Foundry design rules & layout concepts on advanced process nodes.
At least one of the following: Python, Ruby, or Tcl
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
US, Arizona, Phoenix;US, California, Folsom;US, Oregon, Hillsboro
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
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