Job Information
Accenture Silicon Emulation Engineer in Phoenix, Arizona
We Are:
The Silicon Design group is a diverse team of world class silicon engineers. We have 100+ years of cumulative hands-on experience in architecture, logic design, verification, physical design, emulation and firmware. We use the latest silicon technologies and processes to help our clients create well-designed solutions to highly complex challenges. We are designing and developing next-generation, high performance SoCs, supporting our clients in their drive to deliver their product vision to their users. We are involved in all aspects of chip design from definition and architecture through to verification and signoff. Accenture engineers are true “Silicon to SW” Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market.
You Are:
An experienced Emulation and Prototyping Engineer
The Work:
Port ASIC and IP RTL code to prototyping and emulation platforms ( Emulation platforms: Zebu/HAPSs, Palladium/Protium)
Build model from released RTL
Generate loadable image(s) for target prototyping and emulation platform
Run sanity tests to qualify release of the image(s)
Release the emulation/prototyping images to various teams doing functional validation, firmware development and design verification
Assist debug of failures with stakeholder by providing instrumented models and captured waveforms extracted from in-circuit debug logic
Coordinate with EDA and prototyping tools team to validate implementation flows
Here’s what you need:
A minimum 2 years of experience in Simulation, Emulation, Prototyping or FPGA design and verification using System Verilog/Verilog/VHDL
A minimum of 2 years of experience with ASIC/IP RTL to Emulation platforms: Zebu / HAPSs, Palladium/Protium
Bachelor’s Degree or equivalent (12 years) work experience (If an, Associate’s Degree with 6 years of work experience)
Bonus points if:
Good knowledge of SoC design methodologies and technologies, with experience in the complete design validation cycle
Good knowledge of RTL synthesis, mapping RTL to FPGA-based platforms, Unix/Linux development environments and scripting languages like Tcl, Python, C-shell
Working knowledge of C/C++ is a plus
Knowledge of key protocol’s like PCIe, USB, Ethernet, AMBA, UART, DDR, flash memories and their usage in SoC environments is a plus
Compensation at Accenture varies depending on a wide array of factors, which may include but are not limited to the specific office location, role, skill set, and level of experience. As required by local law, Accenture provides a reasonable range of compensation for roles that may be hired in California, Colorado, District of Columbia, Maryland, New York or Washington as set forth below.We accept applications on an on-going basis and there is no fixed deadline to apply.
Information on benefits is here. (https://www.accenture.com/us-en/careers/local/total-rewards)
Role Location Annual Salary Range
California $73,000 to $220,400
Colorado $73,000 to $190,400
District of Columbia $77,700 to $202,700
New York $67,600 to $220,400
Maryland $67,600 to $176,300
Washington $77,700 to $202,700
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Requesting An Accommodation
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Candidates who are currently employed by a client of Accenture or an affiliated Accenture business may not be eligible for consideration.
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